Hi All,
Feedback Stability FAQ Project
ABSTRACT
This "installment" analyzes a conventional Williamsom Amplifier to provide
insight into an already "compensated" feedback amplifier. Using the
"Dynaco Modified Williamson" amplifier as an example, we'll go through a
fairly simple analysis of this amplifier. This installment is NOT
intended to teach you how to compensate a feedback amplifier, but provides
some familiarity for later installments, as it walks through an already
compensated and *proven* design.
The schematic is available at http://www.triodeel.com/dynawil1.gif
We will discuss power supply considerations, then analyze the DC operating
points of the amplifier, identify the feedback networks, determine stage
gains, find the low and high frequency poles and zeros of the amplifier,
discuss how the amplifier is compensated, determine the ammount of
feedback used, and the expected stability of the amplifier.
Although this can be done "engineering wise" using SPICE or various CAE
tools, this approach is not taken; rather, the amplifier is very simply
analyzed so that the audience, who are NOT expected to be practicing
engineers, can use this as a "real" example. As such, there will be some
minor errors, as would be expected from a simple analysis. However, the
end result is reasonably close to reality.
BACKGROUND
As was hinted at in the abstract, the methodology I will use to go through
the analysis is to first review the power supply, in order to determine if
this can be considered a DC source and ignored for AC considerations. We
will then find the operating points of the various gain stages, as that is
needed to determine gain and impedance levels. We will identify "blocks"
to analyze, which will determine what the feedback networks are. We will
then determine the midband gain of the amplifier, both open and closed
loop. (This also tells you how much feedback is being applied). We will
determine the low and high frequency poles and zeros of the amplifier.
Finally we will discuss how the feedback to the amplifier is accomplished,
and discuss the open and closed loop performance of the amplifier.
POWER SUPPLY
The main power supply is a full wave tube rectifier, feeding a CLC filter
section and a second LC filter section. The rectifier etc will have a
output resistance of a few hundred ohms. Therefore, the first LC filter
section "resonates" at 16 Hz with a Q of about 5, causing the impedance
of this filter to be over 1000 ohms at 16 Hz. This will be decreased by
the input impedance of the second LC filter, which is resonant at 11 Hz,
with a Q of about 10. The net effect is the supply will wiggle around
substantially when the circuit is attempting to reproduce 8 Hz. (Not that
it would, but this can affect stability if the feedback network causes
the system to go through unity gain at this frequency.)
The second LC filter will cause a few thousand ohm impedance to be
presented to the driver and input stages at 16 Hz. Since the load
impedances are substantially higher than this, there is probably minimal
effect on system stability, since this cannot change the stage gains by
anything substantial. Note, however, that if the loads were much lower,
we would have to take this into account.
It should be noted that the effects of power supply on the operation of an
amplifier, particularly with feedback applied are sometimes forgotten,
with sometimes not-so-good results. By the way, if the tube rectifier were
replaced with silicon, the lower output impedance would raise the Q of the
LC circuit, potentially causing additional problems. THIS point is often
missed during "upgrades", and can lead to disapointing results.
DC OPERATING POINTS
The output stage is ultra-linear, running 450 volts on the anode and g2,
biased at -35 volts. Contrary to Mullard's recomendations, there is no
series g2 resistors. This stage will draw about 50 mA quiescent current,
which is probably OK. AB1 operation is assumed (grid NOT driven positive).
The driver stage is a push-pull class A 6SN7 stage. Drawing the load line
shows the bias is 4 volts, a current (per section) of 5.5 mA, and a plate
voltage of 150 volts (Vp=150, Vg=0, Vk=4). Under these conditions, the
6SN7 has a gm of 2.5 mS, and an rp of 8000 ohms. Note that the 47k load
resistors will be dissipating about 1.5 watts.
The input stage draws about 4 mA, with 2 volts bias, for a plate voltage
of 90 volts. (Vp=90, Vg=0, Vk=2). Under these conditions, the 6SN7 has a
gm of 2.3 mS and an rp of 8.7k. Due to the unbypassed cathode, the
effective output resistance is about 17.4k ohms. Note that the voltage at
the junction of the 20 uF, 47k and 33k will have about 288 VDC on it.
The phase inverter operates with about 4 volts bias and 4 mA current.
This puts 94 volts on the cathode, 90 on the grid, and 232 volts on the
plate. There will be 326 volts at the junction of the 20 uF and the two
22k resistors. For a split load phase inverter the output resistances are
unequal: the cathode side is (Rk*(rp+RL)/(rp+RL+Rk*(mu+1)) = 1.3k and the
anode side is (RL*(rp+Rk*(mu+1)))/(rp+RL+Rk*(mu+1)) = 20k.
GAIN STAGES - AMPLIFIER MIDBAND GAIN
The output stage, since it already incorporates some level of feedback
because of the "ultra linear" approach, is a little tricky, so we use a
different technique. As this produces about 55 watts, at full power, there
is about 30 volts developed at the 16 ohm tap. With 35 volts of bias,
assume 24 volts RMS produces this. (1.4x25 = 35). At the output XFMR
PRIMARY, this will be about 240 VRMS, so the EL34s are operating with a
gain of 10, and a circuit gain from grid to "speaker" of 1.25 (2 dB).
The 6SN7 driver stage, because it is class A, has no AC voltage on the
cathode, so the stage gain is simply gm*Rl where gm is 2.5 mS and Rl is
8k parallel with 47k, parallel with 100k, or 6.4k, for a stage gain of
16 (24 dB).
The phase inverter produces a gain of roughly .98, which is close enough
to 1. (0dB gain).
There are 2 "gain issues" with the input stage, as this is the connection
point to the global feedback network. The gain from the grid to plate is
(47k parallel 8.7k)/(470+(1/gm)) or 8 (18 dB). The gain from cathode to
plate (which is the global feedback tap) is about 9 (more or less 1 + g-p
gain) (19 dB).
Notice that the main feedback components (100 pF, 10k and 82 pF) have been
ignored. There are 2 feedback loops. The 10k 82pF from output to input
wants to make the closed loop midband "loop gain" 10k/(470 parallel 1/gm)
or about 45 (33 dB). This would be the closed loop gain, cathode-output,
with "infinite" open loop gain. The open loop loop gain is 9*16*1.25=180
(45 dB). Thus, the circuit has about 12 dB of global midband feedback.
Also notice that the "minor" loop caused by the 100 pF capacitor would
want to make the closed loop gain 6.4k/(470 parallel 1/gm) or about 28
(29 dB). More on this later.
The overall open loop gain in the midband input to output is 8*16*1.25=160
(44 dB). The closed loop gain will be about 33 dB, so the sensitivity for
full power output is slightly lower than 0.7 volts.
LOW FREQUENCY POLES AND ZEROES
The first stage has a low frequency pole-zero pair due to the 20 uF in
the plate circuit. This produces a small boost in low frequencies, as the
first stage has slightly more gain at "DC" than it does when the 20 uF is
effective. At DC the stage gain is (8.7k parallel 80k/(470+1/gm)) or 8.6
(19 dB). The 1 dB "lift" occurs at about 0.5 Hz.
The phase inverter bottom side has a zero at DC and a pole at 1.3 Hz. The
top side has this same set and one additional pole-zero pairs due to the
20 uF capacitor. At very low frequencies, there is actually 6 dB of gain
on the plate side of the phase inverter, as the plate load is 44k instead
of 22k. The pole is at .36 Hz, the zero is at .72 Hz. This is a distortion
producing mechanism at very low frequencies, although arguably it is too
low in frequency to be a concern. It may, affect stability and need be
accounted for. (It may be worthwhile to place a 300 volt zener across the
20 uF cap to eliminate this additional pole-zero).
The driver to output is a pole-zero combination as well. The pole is at
6.4 Hz, the zero is at 0.64 Hz. (Caused by the 1 meg in parallel with the
0.25 uF coupling cap.) Note that this is a nice trick that aids stability
at low frequencies.
As there is no AC voltage at the junction of the 100k resistors in the
EL34 grid path, the 40 uF does not contribute to the amplifier response
or stability. (This statement is not true during clipping of for effects
of distortion, which I'm currently ignoring).
The transformer contributes the final low frequency effect. The frequency
is controlled by the impedance level and the primary inductance. For the
A-430 transformer, I couldn't find the constants, but I'll assume an Lp
of 50 Hy, an LL of 4.7 mH, and .5 nF primary capacitance. The loaded LF
pole is therefore at 16 Hz, and becomes the dominant pole.
HIGH FREQUENCY POLES AND ZEROES
There is a pole due to the input resistor and tube capacitance. Using
a gain of 8, the miller capacitance is 32 pF, added to 2 pF Cgk and
6 pF wiring capacitance puts this pole at 400 kHz. Due to the cathode
degeneration, the effective input stage "plate side" resistance is 12.3k.
This produces a pole at about 1.2 MHz.
The cathode follower pole-zeros are again different for the plate side
and the cathode side. At the plate, the effective resistance is 20k
and combined with a 72 pF capacitance (4*16 + 2 + 6) produces a pole at
110 kHz. The cathode side has the same capacitance, but an effective
resistance of about 1.3k ohms, putting the pole at almost 2 MHz which can
probably be ignored. In some sense, this is bad, because the 2 amplifying
paths do not have the same high frequency response, which is a distortion
producing mechanism as well as complicating the feedback issues.
The driver is interesting, since one of the "feedback" capacitors ties to
the bottom driver plate. This causes another "asymmetric" pole, but this
also happens to be the correct phase for negative feedback, and it also
happens to be in the path that "lacked" a high frequency pole in the
phase inverter stage, potentially "compensating" for it. There are 2 pole
frequencies: the upper section is 2 MHz, the lower is 250 kHz.
The EL34 grid circuit is "isolated" by 1000 ohms. The input capacitance
is 11 pF, the miller capacitance is 1.1*10 pF and with wiring the whole
thing is about 32 pF. Against 1k+6.4k, this produces a pole at 670 kHz.
The feedback circuit produces a pole zero pair at 200 kHz and 18 MHz.
The transformer contributes a pair of poles at high frequencies due to
the distributed capacitance and leakage inductance. If I did the math
right, this pair is located at 100 kHz with a Q of about .8, producing
essentially no peaking.
FEEDBACK AND STABILITY ANALYSIS
There are 2 feedback loops to deal with on the high frequency side, due
to the 100 pF between input cathode and driver plate, and from output to
input cathode. There is only one loop to deal with at low frequencies.
On the low frequency side, the good news is that the asymmetries mentioned
in the LF P-Z section occur well after unity loop gain is reached, so do
not significantly affect the low frequency stability. Also there is no
real affect caused by the power supply inductors, as the 8 to 11 Hz
region ends up not being too critical.
The low frequency "bode" plot is described as:
"flat" 45 dB gain to 16 Hz. One pole due to the transformer at 16 Hz.
A second pole due to the output stage grid coupling cap at 6.4 Hz. This
causes the "unity gain" (actually 33 dB gain) point to be reached at
5.6 Hz, providing about 40 degrees of phase margin and/or about 10 dB gain
margin. (This means the feedback could be increased by lowering the 10k
resistor if desired). Note that all lower frequency poles are unimportant.
However, this gain and phase margin is somewhat affected by the power
supply inductors, which are resonant in the 8 to 11 Hz region, so the
stated margins are probably somewhat eroded. Hence it would probably be
unwise to increase the feedback, without "fixing" that problem.
On the low frequency side, the open loop 3 dB point is at 16.5 Hz, and the
closed loop 3 dB point is about 6 Hz.
On the high frequency side the "minor" loop is first analyzed. This is the
loop from the driver plate to input cathode. This would "want" to make the
closed loop gain (1+(6400/470 parallel 435) = 29 or about 29 dB at very
high frequencies. Note this adds a zero to the loop response (loop gain
increases with frequency) but a pole-zero to the closed loop (circuit gain
decreases at high frequencies, until the "pole" is reached).
The HF poles/zeroes to be considered for the minor loop are 1.2M for
the input plate, 2M for the phase inverter cathode, 110k phase inverter
plate, cross coupled to the driver cathode the zero at DC and pole at
250 kHz. The "open loop" gain is 9x.98*16 = 141 (43 dB), the "closed loop"
is 30 dB. Plotting this out puts the "unity gain" point at 470 kHz with
the next dominant pole at 1.2 MHz. There is p l e n t y of gain and
phase margin.
From an overall amplifier view, the effect is an amplifier with a pole at
63 kHz (which is the LF 3 dB point of the minor loop) and a zero at
470 kHz, and more effects at 1.2 MHz, 2 MHz etc.
The global HF path is open loop 45 dB, closed loop 29 dB, pole at 63 kHz,
2 poles at 100 kHz (approximation-this is a pole pair not on the jw axis),
zero at 200 kHz, zero at 470 kHz, pole at 670 kHz, pole at 1.2 MHz, pole
at 2 MHz etc.
Plotting this out shows the 3 dB point at 150 kHz with about 30 degrees of
phase margin and about 9 dB amplitude margin. Fair stability. However,
this is strongly controlled by the transformer, and the A-430 may perform
substantially better than my "model". The stability looks like it could
be improved by changing the minor loop 100 pF cap or the global feedback
82 pF to slightly higher values.
Conclusions
The Dynaco modified Williamson appears to be stable and compensated OK.
There is about 14 dB of feedback. We have found a couple of potential
"improvements". We have seen the effects of transformer on the stability
of an amplifier, and we have seen the importance of power supply operation
in its effects on amplifier performance.
Note that the analysis given is simplified so that anyone with some
determination can follow this report as an example and analyze their own
potential design. The results shown here are not *exactly* correct, as
I've simplified the analysis as much as I could. However, they are close
enough to provide useful data.
Regards,
Steve